The present invention relates to a semiconductor device and a method for fabricating the semiconductor device.
A DRAM (Dynamic Random Access Memory) is a semiconductor memory device comprising cells each including one transistor and one capacitor and which can be large-scaled and highly integrated, and various structures of the DRAM have been conventionally proposed.
The general structure of the DRAM will be explained with reference to FIG. 41. FIG. 41 is a sectional view of the general DRAM cell.
A cell of the DRAM is constituted by one MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and one capacitor. The capacitor is constituted by a storage electrode 128, a dielectric film 130 and an opposed electrode 132. The storage electrode 128 is connected to the source/drain diffused layer 112 of the MOSFET. A bit line 120 is connected to the source/drain diffused layer 110.
A charge stored in the capacitor is outputted to the bit line by turning on the MOSFET and is amplified by a sense amplifier (not shown) to be judged a signal "1" or "0".
However, a charge stored in the capacitor decreases by leak current mainly due to the p-n junction. Accordingly, the so-called refresh operations of rewriting a signal of the cell at a certain time interval are necessary. With a short data retention time of the cell, frequent refresh operations are necessary with a result of large electric power consumption. Thus, it is important for the DRAM that a large interval between the refresh operations, i.e., respective cells have a long data retention time.
Then, a method for fabricating the general DRAM will be explained with reference to FIGS. 42A-42D and 43A-43C. FIGS. 42A-42D and 43A-43C are sectional views of the general DRAM in the steps of the method for fabricating the same, which shown the method.
First, a device isolation film 102 of a thick oxide film is formed on a p-type silicon substrate 100 by LOCOS (LOCal Oxidation of Silicon) to define an active region 104. A p-well may be formed in the silicon substrate 100 before or after the device isolation film 102 is formed.
Then, a gate oxide film 106 is formed in the active region 104 by thermal oxidation, and then a conducting layer of a laminated film structure of, e.g., polycrystalline silicon and metal silicide which is to be a gate electrode 108 is grown and is patterned to form the gate electrode of a MOSFET. The gate electrode 108 also constitutes a word line.
Subsequently, an n-type diffused layer which is to be a source/drain diffused layer 110, 112 is formed by ion implantation. For example, phosphorus (P) ions are implanted at 30 keV acceleration energy and a 2.times.10.sup.13 cm.sup.-2 dose (FIG. 42A).
Then, an insulation film is grown on the entire surface and is etched by RIE (Reactive Ion Etching) to form a spacer 114 on the side walls of the gate electrode 108 (FIG. 42B).
Next, an insulation film 116 is formed on the entire surface, and a contact hole 118 is formed on one of the source/drain diffused layer 110. The insulation film 116 functions as an inter-layer insulation film.
Subsequently, a bit line 120 connected to the source/drain diffused layer 110 through the contact hole 118 is formed (FIG. 42C).
Then an insulation film 122 is formed on the silicon substrate (FIG. 42D), and a storage electrode contact hole 124 is opened on the other source/drain diffused layer 112 (FIG. 43A). The insulation film 122 functions as an inter-layer insulation film.
Next, with the insulation film 122 as a mask, n-type impurity ions are implanted in the silicon substrate immediately below the storage electrode contact hole 124 to form a diffused layer 126.
Subsequently, a storage electrode 128 connected to the source/drain diffused layer 112 through the storage electrode contact hole 124, a dielectric film 130 and an opposed electrode 132, and a capacitor constituted by the storage electrode 128, the dielectric film 130 and the opposed electrode 132 is formed.
Thus, a memory cell comprising one transistor and one capacitor is formed.
Then, an insulation film 134, a metal interconnection 136, a cover insulation film 138, etc. are formed, and the DRAM shown in FIG. 41 is formed.
The capacitor formed thus stacked on the MOSFET is called a stacked capacitor.
Techniques for implanting n-type impurity ions into the substrate immediately below the storage electrode contact hole 124 after the storage electrode contact hole 124 is opened are described in, e.g., Japanese Laid-Open Patent Application No. 06-61451 and Japanese Laid-Open Patent Application No. 09-69616.
In Japanese Laid-Open Patent Application No. 06-61451, in the contact between the storage electrode 128 and the silicon substrate 100, the impurity diffusion is unstable from the storage electrode 128 into the silicon substrate 100, depending on a state of the interface, with a result that a data retention time becomes short. As means for solving this problem, the technique of implanting in advance impurity ions in the silicon substrate 100 in the storage electrode contact hole 124. This corresponds to the diffused layer 126 in the method for fabricating a semiconductor device shown in FIGS. 42A-42D and 43A-43C.
Japanese Laid-Open Patent Application No. 09-69616 discloses the technique of retaining an impurity concentration low below the storage node by an impurity implanted through the storage electrode contact hole 124 to make a concentration gradient blunt, whereby an electric filed intensity at the junction is mitigated to obtain improved data retention characteristics. It is already known in, e.g., Japanese Laid-Open Patent Application No. 06-61486 that an electric field of the storage node is mitigated to thereby obtain improved data retention characteristics.
Japanese Laid-Open Patent Application No. 62-238661 discloses the art of forming an n-type diffused layer of a low concentration below a heavily doped n-type diffused layer.
However, the above-described conventional semiconductor device structures and the method for fabricating the same are insufficient in the following points to make the data retention time of the capacitor long.
Firstly, by simply implanting ions through the storage electrode contact hole 124 the above-described two problems, i.e., the unstable impurity diffusion from the storage electrode 128 into the substrate due to interface states, and the electric field mitigation of the storage node cannot be solved.
Secondly, the technique of implanting ions through the storage electrode contact hole 124 cannot mitigate the electric field only immediately below the storage electrode contact hole 124. However, junction leak, which causes decrease of a data retention time can occur in all the diffused layer. Accordingly, decrease of the junction leak only immediately below the storage electrode contact hole as in the above-described conventional semiconductor device fabrication method is still insufficient.
Japanese Laid-Open Patent Application No. 62-238661 discloses a lightly doped n-type diffused layer is provided but does not detail its arrangement. If the lightly doped n-type diffused layer is provided by photolithography using a resist film as a mask, the lightly doped n-type diffused layer is displaced due to displacement or other causes of the photolithography, which rather causes device disuniformity.